Welcome！[Sign In] ！[Sign Up]！
Front-page it | Collect it | [中国-简体中文]
FAQ Fav
Location:
Search - FPGA uart

Search list

[VHDL-FPGA-Verilog] UART

Description: 输入时钟20M，波特率为9600，实现串口收发功能，通过修改内部分频系数可实现其它波特率的收发-Input clock 20M, the baud rate for 9600, Serial transceiver functions, by modifying the frequency of some other baud rate coefficient can realize the transceiver
Platform: | Size: 7168 | Author: 杨启勇 | Hits:

[VHDL-FPGA-Verilog] gh_uart_16550_080407

Description: FPGA开发中常用的串口模块，经过本人调试，非常实用-Commonly used in FPGA development serial module, after I debug, very useful
Platform: | Size: 16384 | Author: libin | Hits:

[VHDL-FPGA-Verilog] UART_send

Description: Verilog HDL 串口发送程序，在ACTEL Fusion FPGA上实验成功 ，和大家一起分享！^_^-Verilog HDL send serial procedures, ACTEL Fusion FPGA in the success of the experiment, and share with everyone! ^ _ ^
Platform: | Size: 1024 | Author: whq | Hits:

[VHDL-FPGA-Verilog] UART_rec

Description: verilog 串口接收程序，在ACTEL Fusion FPGA上实验成功 和大家一起分享！^_^-Verilog serial receive process, ACTEL Fusion FPGA in the experimental success and share with everyone! ^ _ ^
Platform: | Size: 1024 | Author: whq | Hits:

[Software Engineering] fpgadesign

Description: FPGA/CPLD数字电路设计经验分享，有助于设计能力提高-FPGA/CPLD digital circuit design experience to share, contribute to the design capacity to improve
Platform: | Size: 837632 | Author: 小武 | Hits:

[VHDL-FPGA-Verilog] HCIUART

Description: 蓝牙HCI—UART与并口的FPGA控制接口设计-Bluetooth HCI-UART and parallel port control interface of the FPGA design
Platform: | Size: 102400 | Author: 陈臣 | Hits:

[VHDL-FPGA-Verilog] uart_regs

Description: UART串行通讯FPGA实现，新手上道请多多指教-FPGA realization of UART serial communication, and newcomers on the Road, please advice
Platform: | Size: 1173504 | Author: swisky | Hits:

[VHDL-FPGA-Verilog] uart

Description: 用vhdl实现的串口通信程序,可以综合并下载到FPGA运行.-Achieved using VHDL serial communication procedures, can be synthesized and downloaded to the FPGA to run.
Platform: | Size: 3072 | Author: liaocongliang | Hits:

[VHDL-FPGA-Verilog] uartfifo

Description: FPGA串口代码实现，带串口模块控制程序-Realization of UART in FPGA, with UART module control codes.
Platform: | Size: 565248 | Author: 杨文斌 | Hits:

[VHDL-FPGA-Verilog] uart

Description: 基于FPGA的uart源代码，异步串行通信，vhdl书写的。-uart codes。write with vhdl.
Platform: | Size: 280576 | Author: 陈 | Hits:

[VHDL-FPGA-Verilog] kp_uart

Description: This UART and LCD interface C code Tested on Sparton 3 xilinx FPGA.-This is UART and LCD interface C code Tested on Sparton 3 xilinx FPGA.
Platform: | Size: 3072 | Author: bhagwan | Hits:

[Embeded-SCM Develop] CPLD_UART

Description: 基于FPGA CPLD设计与实现UART,一听名字就知道，不用再说了吧，-FPGA CPLD-based Design and Implementation of UART, a name, we know that you do not say any more,
Platform: | Size: 1024 | Author: 何力 | Hits:

[VHDL-FPGA-Verilog] FPGACPLD

Description: FPGA数字电子系统设计与开发实例导航> 一书的代码，FPGA数字电子系统设计与开发实例导航,用硬件描述语言编写的，I2C,UART,USB，VGA，CAN-BUS，网络等等的书籍配套原代码。。。。使用方法： 1.拷贝到硬盘。 2.用ISE创建项目，分别加入各个代码文件，即可
Platform: | Size: 175104 | Author: bbc | Hits:

[VHDL-FPGA-Verilog] uart

Description: 用FPGA实现uart的verilog源码，包含standard framing error, parity control and overrun detection.-The UART design was designed from a standard uart function with a read/write microprocessor interface. It includes standard framing error, parity control and overrun detection.
Platform: | Size: 2048 | Author: wangyu | Hits:

[VHDL-FPGA-Verilog] Actel_Igloo_nano_UART

Description: This FPGA project include a simple version of the UART for Actel Igloo nano.
Platform: | Size: 453632 | Author: badfox | Hits:

[VHDL-FPGA-Verilog] my_uart_top

Description: 实现的功能如题，就是FPGA里实现从PC接收数据，然后把接收到的数据发回去。使用的是串口UART协议进行收发数据。上位机用的是老得掉牙的串口调试助手-To achieve the functions such as title, that is, to achieve FPGA receives data from the PC, and then receive data back fat. Using a UART serial port protocol to send and receive data. PC using the old tooth out of the serial debugging assistant
Platform: | Size: 3072 | Author: 刘虎 | Hits:

[Software Engineering] xapp341

Description: verilog uart for spartan 3 fpga, its great
Platform: | Size: 21504 | Author: kashif | Hits:

[VHDL-FPGA-Verilog] MCU_FPGA_Interface

Description: msp430单片机用IO口模拟总线时序，与FPGA进行交互的程序，附源代码，verilog，有简单文档。-msp430 I single-chip analog IO bus with timing, with the FPGA interactive process, with the source code, verilog, a simple document.
Platform: | Size: 870400 | Author: 柴佳 | Hits:

[VHDL-FPGA-Verilog] uart

Description: 基于vhdl的串口通信模块，即异步收发机，可实现单片机核fpga的收发串口通信，遵从rs232协议，已经调试过，很不错的资源-Vhdl-based serial communication module, that is, asynchronous transceiver can achieve single-chip transceiver nuclear fpga serial communication, rs232 to comply with the agreement, has been testing, it is a good resource
Platform: | Size: 1024 | Author: 郭帅 | Hits:

[VHDL-FPGA-Verilog] uart_niosII

Description: 基于FPGA芯片，在Nios II IDE软件的开发环境下写的NIos II 软核uart源代码！-Based on FPGA chip, the Nios II IDE software development environment written in NIos II soft-core uart source code!
Platform: | Size: 348160 | Author: 陈涛 | Hits:
« 1 2 ... 5 6 7 8 9 1011 12 13 14 15 ... 26 »

CodeBus www.codebus.net